1. Field of the Invention
The present invention relates to a correlator and despreading code switching method applicable to a matched filter used in a synchronization acquisition in a spread spectrum communication system.
2. Description of the Related Art
A configuration of a conventional matched filter is explained with FIG. 1. The matched filter illustrated in FIG. 1 is an example of a matched filter for 5 times spreading with FIR digital filter.
The matched filter includes shift register 8 composed of reception signal input terminal 1, clock signal input terminal 2 and flip-flops 3 to 7, multipliers 9 to 13, adder 14, output terminal 15, hold signal input terminal 16, despreading code input terminal 17, load signal input terminal 18, calculation register composed of flip-flops 19 to 23, and write shift register 30 composed of flip-flops 25 to 29.
A digital signal that is generated by sampling analogue signals (for example, spread spectrum signal) at a sampling frequency of 4.096 MHz is input to reception signal input terminal 1. In addition, the digital signal is a signal of 6 bits synchronized with a signal input from clock signal input terminal 2. The digital signal is input to flip-flop 3, then shifted toward flip-flop 7 in synchronism with a clock. Multipliers 9 to 13 are multipliers of 6 bits by 1 bit, and output signals of 7 bits. Multiplier 9 multiplies an output signal from flip-flop 3 (6 bits) by an output signal from flip-flop 19 (1 bit) from among output signals from calculation register 24. Multipliers 10 to 13 multiply respectively output signals from flip-flops 4 to 7 by output signals from flip-flops 20 to 23 in calculation register 24. Adder 14 adds outputs from multipliers 9 to 13 to output from output terminal 15.
A multiplication procedure in a despreading code switching is explained below with reference to FIG. 2.
In a state before a despreading code switching, it is assumed that output signals from flip-flops 29 to 25 in write shift register 30 are respectively despreading code sequences C-5, C-4, C-3, C-2 and C-1 and that output signals from flip-flops 23 to 19 in calculation register 24 are respectively despreading code sequences C-5, C-4, C-3, C-2 and C-1.
First, the multiplication procedure before the despreading code switching is explained.
A digital signal of first sampling data D0 input to reception signal input terminal 1 is input to flip-flop 3. Multiplier 9 multiplies the sampling data D0 by despreading code C-1. Accordingly multiplier 9 outputs an output signal indicative of a value of D0 xc3x97C-1.
When a digital signal of second sampling data D1 that is input to reception signal input terminal 1 in synchronism with a clock input from clock signal input terminal 2 is input to flip-flop 3, first sampling data D0 is input to flip-flop 4. As a result, multiplier 9 multiplies second sampling data D1 by despreading code C-1, while multiplier 10 multiplies first sampling data D0 by despreading code C-2. Accordingly, multiplier 9 outputs an output signal indicative of a value of D1xc3x97C-1, while multiplier 10 outputs an output signal indicative of a value of D0xc3x97C-2.
Then, the same processing as described above is repeated until fourth sampling data D3 is input.
When a digital signal of fifth sampling data D4 is input to reception signal input terminal 1 in synchronism with a clock input from clock signal input terminal 2, first to fifth sampling data D0 to D4 are respectively input to flip-flops 7 to 3. Accordingly, multiplier 9 outputs a multiplication result indicative of a value of D4xc3x97C-1, multiplier 10 outputs a multiplication result indicative of a value of D3xc3x97C-2, multiplier 11 outputs a multiplication result indicative of a value of D2xc3x97C-3, multiplier 12 outputs a multiplication result indicative of a value of D1xc3x97C-4, and multiplier 13 outputs a multiplication result indicative of a value of D0xc3x97C-5.
According to the above processing, all multiplication needed to obtain the correlation value of digital signals of first five sampling data D0 to D4 respectively with despreading code sequences C-5, C-4, C-3, C-2 and C-1 has been performed. Adder 14 adds a multiplication result from each multiplier, and outputs correlation result H(4) from output terminal 15.
As a result, all despreading calculations needed to obtain the correlation value of digital signals of five sample data D0, D1, D2, D3 and D4 respectively with 5 bits despreading code sequences C-5, C-4, C-3, C-2 and C-1 have been performed.
Next, processing for a despreading code switching in the matched filter is explained. When hold signal input terminal 16 is set at a low level, C0, C1, C2, C3 and C4 input from despreading code input terminal 17 is sequentially input to flip-flops 25 to 29 composing the write shift register in synchronism with the clock input from clock signal input terminal 2. Further, when a signal input from load signal input is a low level, despreading code sequences C0, C1, C2, C3 and C4 in write register 30 are loaded in calculation register 24 in synchronism with the clock input from clock signal input terminal 2.
Since the clock for the despreading calculation and the clock to load the despreading code are both synchronized with the clock input from clock signal input terminal 2, the clocks are affected by delay in a circuit internal, which changes depending on diffusion processes of semi-conductor, environment temperature, supply voltage, etc., thereby making it impossible to specify which moves faster logically.
Hence, when a digital signal of sixth sampling data D5 is input to reception signal input terminal 1, it is not possible to specify the despreading code sequences to be used in the despreading calculation, i.e., to specify which despreading code sequences are used for the despreading calculation, C-5, C-4, C-3, C-2 and C-1 that are the despreading code sequences before the switch, or C0, C1, C2, C3 and C4 that are the despreading code sequences after the switching.
Next, the explanation below describes about an calculation processing after the despreading code sequences C0, C1, C2, C3 and C4 are loaded.
When a digital signal of seventh sampling data D6 is input to reception signal input terminal 1 in synchronism with the clock input from clock signal input terminal 2, third to seventh sampling data D2 to D6 are respectively input to flip-flops 7 to 3. Accordingly, multiplier 9 outputs a multiplication result indicative of a value of D6xc3x97C4, multiplier 10 outputs a multiplication result indicative of a value of D5xc3x97C3, multiplier 11 outputs a multiplication result indicative of a value of D4xc3x97C2, multiplier 12 outputs a multiplication result indicative of a value of D3xc3x97C1, and multiplier 13 outputs a multiplication result indicative of a value of D2xc3x97C0.
According to the above processing, all multiplication needed to obtain the correlation value of digital signals of five sampling data D2 to D6 respectively with despreading code sequences C0, C1, C2, C3 and C4 has been performed. Adder 14 adds a multiplication result from each multiplier, and outputs correlation result H(6) from output terminal 15.
As a result, all despreading calculations needed to obtain the correlation value of digital signals of five sample data D2, D3, D4, D5 and D6, which are 2 samples later than five sample data D0, D1, D2, D3 and D4, respectively with 5 bits despreading code sequences C0, C1, C2, C3 and C4 have been performed. Then, the same processing is repeated.
However, in the configuration of the conventional matched filter described above, as described in the conventional case, the clock with which the despreading calculation register in the matched filter is synchronized and the clock with which the despreading code switching is synchronized are the same, thereby remaining a problem that it is difficult to decide which codes before the switching or after the switching are used in the system that requires a successive correlation detection when the despreading codes are switched.
The present invention is intended to solve the above-mentioned conventional problem. The object of the present invention is to provide a correlator and despreading code switching method capable of detecting the correlation of received signals successively without applying wrong codes when the despreading code is switched, by differing timings of the clock with which the despreading calculation processing in the matched filter is synchronized and the clock with which the despreading code switching processing is synchronized.
The present invention provides a constitution where it is possible to detect the correlation of received signals successively without applying wrong codes, by differing timings of the clock with which the despreading calculation processing in the matched filter is synchronized and the clock with which the despreading code switching processing is synchronized.
The present invention provides an effect that it is possible to perform calculations with specified despreading codes successively without applying wrong codes in depsreading digital signals with a plurality of despreading codes, by differing timings of a despreading calculation of digital signals and the despreading code switching.